It is sometimes desirable to digitize analog signals at higher speed than, but with nearly the same accuracy as, can be obtained from a single analog-to-digital converter (ADC). One approach is to operate a number, N, of individual M-bit ADCs so that they sequentially sample the same analog input signal. We will call these individual M-bit ADCs the “subADCs.”=Suppose each subADC samples at a frequency, fs, and that the samples of the N subADCs are equally spaced apart by a time equal to 1/(N*fs). Then, if the M-bit digital outputs of the N subADCs are interleaved together properly, the input signal is also properly sampled, with the samples converted to digital values at a combined sample rate of Fs=N*fs. In this way a higher equivalent sampling rate can be obtained with nearly M-bit accuracy.
One difficulty with this approach is that the components and operating conditions of the individual subADCs will not be identical. Such differences can lead to spurious energy in the output digital data that is not present in the input analog signal. In the case of two subADCs, each operating at sample rate of fs, a difference in Direct Current (DC) offset between the two sub ADCs will produce a square wave at an output frequency of fs/2, with an amplitude equal to the magnitude of the difference in the offset (i.e., a spurious tone will appear at fs/2).
In certain prior art systems of this type, the offset can be measured at the output of the subADCs, and corrected by a digital adjustment to the digital output samples.
Another approach to reduce the effect of offset is described in U.S. Pat. No. 6,377,195 issued to Eklund, et al. The approach described there is to randomly switch, or “chop” the polarity of the analog input to each subADC before it is sampled and digitized. This polarity-switching process produces an input analog signal with zero mean. The polarity of each sample is then switched back to its original polarity, or “reverse chopped”.